Pipelined analog-to-digital converters (ADCs) may include a series of cascaded ADC stages each of which is responsible for converting a portion of an analog signal into digital codes. The digital codes of all portions of the analog signal may be eventually aligned to form a digital output representing the analog signal. Pipelined ADCs may be used in high-speed and high-resolution analog-to-digital conversion applications because the pipeline may break down the task of analog-to-digital conversion into a series of subtasks that may be performed at high sampling rates. One limitation of pipelined ADCs is that errors at earlier stages that commonly correspond to more significant bits may propagate downstream to subsequent stages. For example, U.S. Pat. No. 7,271,750 (the '750 patent, the content of which is incorporated by reference in its entirety) discusses errors caused by a finite amplifier gain. To correct these errors, the '750 patent introduces error extraction circuits to estimate the finite gain of the amplifier. In practice, the error extraction circuit may run at a slower clock than the high speed clock of the main pipeline. For example, the error extraction circuit may extract errors one out of every M (>=1) clock cycles for the gain estimation. The estimated gain may be used to calibrate the eventual digital output.
One limitation with the system as described in the '750 patent is that the slow clock for error extraction and correction may exert spurious loads on the pipeline, thereby causing spur noise in the digital outputs when the slow clock does occur. The spur noise may constitute an additional source of errors that have not been addressed by the current art. Therefore, there is a need for systems and methods that mitigate the spur noise due to mixed clock speeds in pipelined ADCs.